[Oberon] RISC5 implementation issues.

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> skulski at pas.rochester.edu
> Sent: Monday, 22 February 2016 2:49 AM
> To: oberon at lists.inf.ethz.ch
> Subject: Re: [Oberon] RISC5 implementation issues.
> 
> Magnus wrote:
> 
> > OK, so I decided to try to implement the clocking as Walter
> suggested
> 
> Ou of curiosity: Chapter 10 of the book "FPGA prototyping.." by Pong.
> P.
> Chu is devoted to SRAM interfacing. He is using the same Spartan-3
> board that Paul Reed used. All the timing issues are thoroughly
> analyzed. Three different designs are presented and discussed. The
> book has two versions:
> VHDL or Verilog (two separate books). So I am curious why this
> discussion is not referencing the textbook but rather it is starting
> from scratch?
> 

The External SRAM chapter is Chapter 11 in my (2008) edition of Pong P.
Chu's book. Some of the closing comments in section 11.5.5 Advanced FPGA
Features state:
 
"The memory controller examples in this section illustrate the limitations
of the FSM-based controller and synchronous design methodology"
...
"Due to the variations in propagation delays, he synthesized circuits are
not reliable and may or may not work"
...
"Detailed discussion of DCM and IOB is beyond the scope of this book". 

It is the use of DCM that has been the focus of the recent discussions here.

Regards,
Chris

Chris Burrows
CFB Software
http://www.astrobe.com/RISC5