[Oberon] Fast version of Oberon RISC5 for Pepino

[skulski at pas.rochester.edu]

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From: Chris Burrows [chris at cfbsoftware.com]
There are two versions of Multiplier still available on Prof Wirth's site.
One which is portable (Multiplier.v) and one which uses the fast 18 x 18 bit
multiplier units (Multiplier1.v):

Chris:

Spartan-3 was the first generation that provided the silicon implementing
18x18 multipliers. Since NW code was written for Spartan-3, it is not
surprising that he provided the targeted version of the code.

Subsequent generations added more silicon features inside these blocks,
such as multiply-accumulate registers. The blocks were renamed "DSP
slices". More features are being added to these in every new generation.

Writing Verilog/VHDL code that is portable among these generations may be
tricky. One can adopt Magnus' approach by writing high level code
expressing the intent, and then let the compiler "infer" the proper
circuit. (FPGA compilers do not compile, they "infer" according to the
official slang.) The word "infer" means that the designer should check in
the compilation report whether or not the compiler guessed right, and
change the syntax if not.

My general conclusion is that the FPGA code only pretends to be portable.
Yes, you can write code which looks obvious. No, you cannot assume that
the obvious code is translated according to the intent. You need to check
whether this particular compiler "inferred" the proper circuit for this
particular FPGA.

I am also skeptical about writing code in LOLA, translating to Verilog,
and claiming it is the end of the problem. In my mind LOLA is a sketch of
the final solution rather than the final solution which needs to be
written in the way the vendor recommends. It means VHDL/Verilog.

I also think that having slightly different variants of the code for
various FPGA families cannot be avoided.

Just my experience. Yours may differ.

Wojtek