[Oberon] Volatile variables in Oberon

[Skulski, Wojciech]

Srinivas:

> Do you mean a volatile array?

Yes. In the FPGA the internal RAM is dual-ported. The processor maps the port A in its memory space. The FPGA logic can access the other port B from the fabric space. The data can be written by the fabric to port B, and accessed by the processor from port A. 

Consequently, the array can change without processor's knowledge. Therefore it is volatile. 

This way of interfacing two subsystems inside the FPGA is the most fundamental way of coupling inside the FPGA. It is used all the time. The dual-ported RAMs are present inside the FPGA precisely for this purpose.

I can see how one can use SYSTEM to access such an array. Basically, one will be writing an assembly code using ADR, PUT, and GET. It is certainly doable. I am just asking if there could be a better mechanism, given the fact that the FPGA Oberon System by design is meant for interfacing the processor subsystem to the logic fabric inside the same FPGA. Volatile registers and volatile RAM blocks are the building blocks of such interfaces.

 I can hear the argument that there is no problem because the compiler is not optimizing.  However, it somehow feels not right to me that one cannot simply map the register or the RAM block to the processor space. 

W.



With thanks and best regards,

Yours sincerely,
Srinivas Nayak

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On 08/01/2016 05:01 AM, Skulski, Wojciech wrote:
> Chris wrote:
>
>> It is not allowed in Oberon-07 based systems either e.g. Project Oberon
>> 2013. Oberon-07 is more strict than Component Pascal as it limits the use of
>> pointer variables to record types. Pointers to arrays are not supported.
>
> Not supporting pointers to arrays is surprising for an FPGA-based project. Looking from the hardware side, an array is one of just two fundamental constructs in programmable logic. The other one is a register. Just to clarify, a register can be made out of distributed flip-flops, while an array corresponds to FPGA RAM. (There are two kinds of RAM, the block BRAM and the distributed RAM. For this discussion they are pretty much the same.). There is not much else in the FPGA but these two kinds of objects. I find it surprising that one of them is supported via the SYSTEM put and get, while the other is not.
>
> There is a fundamental need in the FPGA-based project to interface the software to hardware. You can also say "interface the CPU to the logic portion of the design". This can only be done by mapping software objects to hardware objects. Mapping a variable to a register has been discussed in this thread. The solution seems adequate. However, mapping the software array to the hardware array seems to be left out of focus. I can imagine a kluge using PUT and GET, but it will be a kluge.
>
> Component Pascal offered the untagged arrays for much the same purpose. I wonder why a similar solution seems to be missing from the FPGA Project Oberon.
>
> Regards,
> Wojtek
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