[Oberon] RISC5; was Embedded Project Oberon on a breadboard

[Skulski, Wojciech]

Pay attention to the fact that RISCV also exists and it is a completely different beast: https://riscv.org/

Some sort of clarification may be in order.

W

________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of peter at easthope.ca [peter at easthope.ca]
Sent: Saturday, September 10, 2016 11:01 AM
To: oberon at lists.inf.ethz.ch
Subject: [Oberon] RISC5; was Embedded Project Oberon on a breadboard

From:   Chris Burrows <chris at cfbsoftware.com>, Sat, 10 Sep 2016 14:54:09 +0930
> ... ported the Astrobe Embedded Project Oberon RISC5 system ...

Sorry for a trivial question but I wonder about an acceptable
statement of the meaning of RISC5.
"RISC5, the CPU of Project Oberon 2013, implemented in a FPGA."
What is the significance of "5"?

A glossary section in https://urldefense.proofpoint.com/v2/url?u=https-3A__en.wikipedia.org_wiki_Oberon-5F-28operating-5Fsystem-29&d=CwICAg&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=uUiA_zLpwaGJIlq-_BM9w1wVOuyqPwHi3XzJRa-ybV0&m=QEJ7cWEv448eOIejxrF0l5tZoT4HCaSvWRSat8W3yr4&s=SIg4hzb9UaapQhE7NHadbVcNBqemsaoyOcTgqxXiuzo&e=
could be helpful.  RISC is mentioned under History but RISC5
could be in a glossary.  Comments?

Thanks,                     ... Lyall E.
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