[Oberon] RISC5; was Embedded Project Oberon on a breadboard

[Pablo Cayuela]

You could check Wirth's RISC versions here:

https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf
El sept. 10, 2016 7:37 PM, "Pablo Cayuela" <pablo.cayuela at gmail.com>
escribió:

> If you check the progression of CPU construction examples at Niklaus
> Wirth's page, you would see the enumeration of RISC type CPUs made by him.
> That said, the version used for implementing Oberon operating system from
> scratch into an FPGA board, is the fifth version of his RISC CPUs.
>
> Pablo Cayuela
> El sept. 10, 2016 12:04 PM, <peter at easthope.ca> escribió:
>
>> From:   Chris Burrows <chris at cfbsoftware.com>, Sat, 10 Sep 2016 14:54:09
>> +0930
>> > ... ported the Astrobe Embedded Project Oberon RISC5 system ...
>>
>> Sorry for a trivial question but I wonder about an acceptable
>> statement of the meaning of RISC5.
>> "RISC5, the CPU of Project Oberon 2013, implemented in a FPGA."
>> What is the significance of "5"?
>>
>> A glossary section in https://en.wikipedia.org/wiki/
>> Oberon_(operating_system)
>> could be helpful.  RISC is mentioned under History but RISC5
>> could be in a glossary.  Comments?
>>
>> Thanks,                     ... Lyall E.
>> --
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>> http://easthope.ca/Peter.html Bcc: peter at easthope. ca
>>
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>
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