[Oberon] RISC-5 and memory

[Skulski, Wojciech]

Magnus:

  if we accept that RISC5 is carved in stone then we are stuck. However, I am taking the position that neither RISC5, surrounding peripherals, nor the software are carved in stone. Anyone can do anything. I further stipulate that we do not want to do "anything" and we are seeking mutual platform and mutual understanding. The recent type compatibility discussions set an example. On the other hand, things like address range are open to modifications. 

If it so happens that the compiler is enforcing a particular address range that has to be modified, then it needs to get modified. I have not looked at it yet, because there was no need till now. I am delaying this kind of deliberations until they become necessary.

I look at it from the hardware point of view. Your Pipistrello should be perfectly capable to become the next Oberon platform. It has enough memory and it has the HDMI output. If the FPGA Oberon firmware got ported to Pipistrello then we would be in a much better situation. This would imply significant FW modifications. Why not? Firmware is crafted from HDL, which is a subject to be modified.

W.

PS: Today the students launched Pepino. The Oberon screen was running when I arrived. You did good job! They found the proper files, installed, and got running. I showed them how to compile Sierpinski.Mod, Hilbert.Mod, and Stars.Mod. The first two modules ran, the latter ran and then it crashed The System on Stars.Stop. Sometimes The System froze, sometimes it threw a bunch of traps, and sometimes it behaved gracefully. So there is a bug in Stars.Mod. Also, I did not like that the mouse pointer wraps around the screen. t disappears on the left and reappears on the right. It is a "feature". So there is something to be fixed, though the students can live with it for a while. 

A more serious problem was that one student was terrified, while the other did not understand anything. It is not a software problem. It is rather a problem of the US education system.   

________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Magnus Karlsson [magnus at saanlima.com]
Sent: Friday, October 6, 2017 4:30 PM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] RISC-5 and memory

On 10/6/2017 10:53 AM, Skulski, Wojciech wrote:
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of peter at easthope.ca [peter at easthope.ca]
>
>> How many MiB would you want?
> Enough for V4, S3, and Component Pascal running natively on RISC5. I would guess 16 MB should be enough, but more is better.
>
FYI, RISC5 CPU only supports up the 24-bit addresses, i.e. the
architecture is limited to 16 MB address space.  Part of this memory
space is used for I/O and boot-loader ROM.
It used to be that RISC5 only supported 20-bit addresses but NW extended
the address range to 24 bits in the 25.9.2015 version.

Magnus
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