[Oberon] FPGA - Colour Support

[Skulski, Wojciech]

Thomas:

Correction. The chip on my schematic page says "166 MHz". The 200 MHz version exists, but it is not in stock at Digikey. The 166 MHz chips are available. Such a chip can probably be overclocked, but let's not go that route. 

OK, let it be 166 MHz. The 32-bit data can then be read every 166/2 = 83 MHz. This is close to the pixel clock. Let's assume the memory is ran at 150 MHz clock, 75 MHz per transaction. As you can see, taking one byte per pixel will take about 25% of the memory bandwidth. The remaining 75% MHz will allow RISC5 to run at twice the present performance (effectively at 50 MHz), and still not be starved of any bandwidth because pixels will be stolen from memory in the remaining 25% of the channel speed. This is a basic estimate of what will be possible. The HDL code is of course another matter. Someone may want to try by hand (using LOLA ;-), but I would rather recommend one of the proven cores. 

 Correct me if I am wrong.

Thanks,
Wojtek
________________________________________
From: Skulski, Wojciech
Sent: Sunday, October 8, 2017 11:02 AM
To: ETH Oberon and related systems
Subject: RE: [Oberon] FPGA - Colour Support

Thomas:

  I think it makes sense to go step by step. I think that color needs 2 megs at least. I would like to order another Pepino with 2MB, though there is no entry for such an upgrade on the Saanlima page. I also want the largest FPGA that fits the footprint, just in case. Again, there is no option grid on the Pepino page.

I am hesitating whether I should put any more time into my own board with two megs ZBT RAM, or perhaps Magnus can take over this particular route. A 2 meg chip will run with 200 MHz clock and 100 MHz R/W cycle, which is factor four better than the present Pepino design. I think that having such a Pepino++ would put us on a solid path towards 8-bit color.

The schematic page is attached. Magnus, what do you think?

Wojtek


________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Tomas Kral [thomas.kral at email.cz]
Sent: Sunday, October 8, 2017 10:06 AM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] FPGA - Colour Support

Hi Joerg, Wojtek, Magnus, All,

Thanks for all your posts and recommendations.
- 2MB of RAM, something I plan by chip piggy back, while driving upper
  meg with CS, from `Verilog' code.
- overclock to 30MHz

As I have got `Pepino' board with 1MB, and 25Mhz, this can make an
interesting exercise for students.

What I need to solve however first, is how to map b&w screen
in memory completely separate from colour bit planes. This would allow
using `Display.Mod' unchanged while programming colour logic.

In other words, one bit in memory tells if the display pixel is
illuminated or not, the other bit planes, tell if there are also some
colours to add to it.

In the two designs I have got so far, several bits in memory control RGB
of a single display pixel, this results in seeing entire display buffer
duplicated several times on the monitor.

--
Tomas Kral <thomas.kral at email.cz>
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