[Oberon] FPGA - Boot over serial line

[Skulski, Wojciech]

Magnus:

  I stand corrected concerning the boot loader. 

About a year ago we looked into converting the bootloader into a standalone application which would run embedded and never load the actual system. Our goal was "PicoBlaze on steroids", if you forgive the pun. This was in line with what Chris is doing. Just use the RISC5 as a deeply embedded microcontroller running its code off BRAM. It worked pretty well.

This lets me wonder if we do not want to pack the speed-critical parts into a module, lock it into BRAM, and let it stay there forever. This could be legitimately named a kernel. The rest of the system would execute from RAM. Doing so would let RISC5 run faster while executing code from BRAM, and let it be slowed down via the stall mechanism, while reaching to RAM. I think that all the mechanisms for this are basically ready. 

Do you think it makes sense? Some parts of the system must be more heavily used than others. These are good candidates to be locked into BRAM.

W.


________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Magnus Karlsson [magnus at saanlima.com]
Sent: Sunday, October 15, 2017 6:56 PM
To: ETH Oberon and related systems
Subject: Re: [Oberon] FPGA - Boot over serial line

Wojtek,

This is the bootloader code, you would need to modify it before the bootloader runs.  After boot this code is not used.

As for ISE, it's the only way to synthesize code for Spartan 6, Vivado is used for the 7 series FPGA and on.

Magnus

> On Oct 15, 2017, at 9:48 AM, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>
> I wonder if there is a way to use ChipScope to write directly to the BRAM while the Oberon System is running. The CPU would need to be stopped before doing this (stalled, perhaps), and then restarted from the known BRAM location after the updating was done.
>
> Any thoughts?
>
> Wojtek
> ________________________________________
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Magnus Karlsson [magnus at saanlima.com]
> Sent: Sunday, October 15, 2017 12:33 PM
> To: oberon at lists.inf.ethz.ch
> Subject: Re: [Oberon] FPGA - Boot over serial line
>
> It will also take .mem files (-bd FILENAME [<.elf>|<.mem>]).  The
> example has .elf since that's the most common format directly generated
> by the compiler.
>
> You will need to find the location of the block RAM used to hold the
> boot code.  The location can be found out using a tool inside ISE called
> "FPGA editor" that will allow you to inspect the final logic placement
> inside the FPGA.  In case of the RGB/mono bit file I sent you, the
> location is RAMB16_X0Y20
>
> Magnus
>
>
>> On 10/15/2017 12:16 AM, Tomas Kral wrote:
>> On Fri, 13 Oct 2017 11:05:31 -0700
>> Magnus Karlsson <magnus at saanlima.com> wrote:
>>
>> Hi
>>
>>> In our case the prom.mem
>>> data is stored in one of the 32 block rams available in the Spartan6
>>> LX9 so you would need to find out which one the synthesis toll
>>> decided to use for this purpose.  The Data2Mem tool needs this
>>> information in a special file called .bmm that will also specify how
>>> the memory is organized (in our case it's organized as 32 bits x 512
>>> words).
>> The syntax is:
>> $ data2mem -bm my.bmm -bd code.elf -bt my.bit -o b new.bit
>>

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