[Oberon] FPGA - nRF24L01 `RPI Net' server

[Tomas Kral]

On Fri, 4 May 2018 17:49:21 +0200
Jörg <joerg.straube at iaeth.ch> wrote:

> The chip is able to tell you when it received a packet and it can
> tell you when it sent the packet.

Yes, I agree. This is what I actually try to do, but in time waiting
loops. As the bits, in my opinion need be polled, with some
delays, defined loop timeouts and retries.

This is my understanding of chip operation so far.

The chip provides two specific registers to control dataflow across RX
and TX FIFO pipes:

STATUS and FIFO_STATUS.

STATUS bits RX_DR(data ready), TX_DS(data sent)
FIFO_STATUS bits RX_EMPTY(FIFO empty)

To check for incoming data, we can poll either RX_EMPTY bit, or RX_DR,
or both.

When sending data TX_DS can be checked, if transmission successful.
Also TX_DS need be cleared if high, telling auto acknowledgement ACK
was received. Auto-retry / auto-acknowledgement is default chip
setting feature. ACK packets are sent outside FIFO, in defined time
windows, when receiver and transmitter temporarily switch their roles. 

The common receive operation is easier to implement. While transmit
operation can use more strategies, as we need to also check TX_FULL
(surprisingly offered in both registers), as FIFO may fill up, not
accepting further outgoing data, waiting for the receiver end to
consume its data queued in RX FIFO. 

This is when communication may appear blocked, as one end keeps
resending until success, not getting it, while the other end is not yet
listening or no longer listening => loop timeouts and retries. 

I was surprised to see, that to get a packet through passing CRC
check, and receiving ACK, typically quite a few retransmitions are
needed. We can here rely on auto-retransmit chip feature (set in
SETUP_RETR) or toggle TX_REUSE transmit bit in program.

Am I close?

-- 
Tomas Kral <thomas.kral at email.cz>