[Oberon] Oberon board availability (was Moving oberon to RISCV?)

[Skulski, Wojciech]

Magnus wrote:

>Or you could buy a new Pepino Oberon Kit from Saanlima Electronics with
>an Oberon system ready to go, just add monitor, keyboard, mouse and USB
>cable.  The kit is normally $104.95 but is currently on sale for 20% off
>(use coupon OberonGo at checkout).

Excellent. I am glad you are pointing it out. We have one such Pepino board. It is working very well. I will add the pointer to the RiskFive website.

So I should explain the difference between Pepino and RiskFive.

1. RiskFive kit is 10x more costly than Pepino. (OK, at this point we have lost all the customers ;-)

2. Pepino aims at running the original 2013 Oberon System. RiskFive was designed to advance the Oberon System beyond the current status.

3. Pepino + Oberon just works and it is ready to go. RiskFive lacks any working FW at this point, because it intentionally provides new, high performance hardware. The FW and the corresponding SW drivers need to be developed.

4. FW/SW developments are of course possible with Pepino, but there is no nagging reason to pursue such modifications because Pepino just works. It is also not clear, what these modifications should be, because "don't fix it if it ain't broken". In case of RiskFive, its FW/SW *must* be fixed because it does not even exist yet.

5. RiskFive is a development platform for non-Oberon applications as well. It can accommodate FPGAs up to Artix 100T, which is sufficient for RISC-V. (Any takers?) Soldering Artix 100T will boost the kit to some $1,200. But hey, if you want to betray Professor N.Wirth and go to the Berkeley bunch instead, then you deserve the punishment. 

6. Pepino has a rather limited set of GPIO pinned out to 0.1" headers. These are good for the low and mid-performance apps like pushbuttons, PWM, and so on. In case of RiskFive, all the pins that are not occupied for ZBT, were pinned out to high performance Hirose connectors with integral ground. (Most were routed differentially.) These can be driven at the full speed that Artix can deliver, which is over 1 gigabit per second per pair. 

7. Pepino is a closed ended design. RiskFive is open ended in the sense that the end-user functions are on the motherboard which is relatively easy to modify. (I will post the design files.) The division between the high-performance core module and the user-mode motherboard is intentional. The core module is "just the FPGA", memory, boot flash, and power. All the application stuff is on the motherboard which is meant to get modified.

8. Pepino cannot provide a rich multicolor display due to limited RAM. Four colors are the limit. (Magnus has implemented the four color display. Many thanks!) RiskFive has enough RAM to support 1k*768 (or even slightly larger) of 8-bit pixels, mapped to 24 bit color via a lookup table. (A palette.) It was one of the main goals driving this design. Note that the video is on the motherboard, what hints that some planned applications will be deeply embedded w/o the display. Ditto with the mouse and keyboard.

9. Another hint at such deeply embedded application is the presence of GbE PHY on the core RiskFive module. This PHY is not planned to be used with Oberon, unless we can find some really brave soul to implement the Ethernet MAC in the fabric and the Internet stack in Oberon. I am not counting on this. The PHY is meant for software-less apps outside the Oberon realm. 

10. Pepino can run RISC5 at 25 MHz. The clock speed is limited by the ASRAM chip. It is the same performance as the original 2013 Oberon, and for he same reason. This limitation is lifted in RiskFive, whose synchronous RAM can be clocked up to 250 MHz. I will push my interns to achieve 100 MHz RISC5 operation. Faster operation is allowed by the ZBT memory and we can try pushing even beyond 100 MHz.

11. In summary, RiskFive is definitely not "ready to go". It is an adventure which is just beginning. I hope that the journey will continue.

Thank you,
Wojtek