[Oberon] Arduino MKR Vidor 4000 (was New Hardware for Oberon / Risc-5 ?)

[Jan de Kruyf]

I don't know whether I kick in an open door, but this just passed my eye:

https://www.crowdsupply.com/sifive/hifive1

It would be a very interesting RISC-V processor / board running Oberon for
my purposes.

cheers,

J.


On Sat, Jul 28, 2018 at 5:52 PM, Peter Matthias <petermatthias at web.de>
wrote:

> CPU-cache can be independent from the instruction set. I think
> Risc-V/Arduino groups should be asked if there will be a RISC-V port. If
> yes, RISC5 port should also be possible or RISC-V can be used directly (or
> the ARM part of the board).
>
> Peter
> --
> sent mobile by neffos
> Am 27.07.18, 11:21, "Jörg" <joerg.straube at iaeth.ch> schrieb:
>>
>> Simple porting of the RISC-5 willl be difficult to that board as this CPU
>> does not support a cache. First as Wojtek correctly pointed out, it‘s
>> SDRAM, but secondly the AS4C4M16SA-7BCN is organized as 16x 4Mb.
>> Good, let’s assume the RISC-5 would evolve to RISC-6 adding an
>> instruction and a data cache to overcome the longer SDRAM start time until
>> full transfer speed is reached, this cache has to be used as well to make
>> it look like a 32 bit architecture.
>>
>> Jörg
>>
>> > Am 27.07.2018 um 03:43 schrieb Skulski, Wojciech <
>> skulski at pas.rochester.edu>:
>> >
>> > Markus wrote:
>> >
>> >> Arduinio brought a brand new FPGA board to the market!
>> >> Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM
>> >
>> > The website says "onboard 8 Mbyte SDRAM". SDRAM is not SRAM. It is hard
>> to say for sure what they installed because neither the schematic nor the
>> BOM are prominently displayed on that website. Maybe they are there
>> somewhere. But I assume they know what they are saying.
>> >
>> > I cancelled my previous Oberon board project after realizing the
>> intricacies of caching. I do not want to say that SDRAM is bad. But I
>> decided to shy away from it. Another concern is indeterministic software
>> execution time, depending on the cache status and thus on execution
>> history. This would be bad for my field of study.
>> >
>> > www.arduino.cc/en/Guide/MKRVidor4000
>> >
>> > Wojtek
>> >
>> > --
>> > Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related
>> systems
>> > https://lists.inf.ethz.ch/mailman/listinfo/oberon
>>
>> --
>> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
>> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>
>
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