# [Oberon] FPGA - Display.Mod 4-bit colour

Jörg joerg.straube at iaeth.ch
Thu Oct 18 13:58:22 CEST 2018

```Tomas

If you want to know how to program your video correctly you have to study your HW.
As I have another board (Pipistrello) as you have (Pepino) I can not send you my Verilog code as your HW is different.

If you look at your „RISC5_pepino.ucf" you will find:

NET "RGB[0]" LOC = "B10"; # RED 0
NET "RGB[1]" LOC = "A10"; # RED 1
NET "RGB[2]" LOC = "C11"; # RED 2
NET "RGB[3]" LOC = "A11"; # GREEN 0
NET "RGB[4]" LOC = "B12"; # GREEN 1
NET "RGB[5]" LOC = "A12"; # GREEN 2
NET "RGB[6]" LOC = "C13"; # BLUE 0
NET "RGB[7]" LOC = "A13"; # BLUE 1

So, the lowest three bits (0..2) are red, bits 3..5 are green and the most significant two (6..7) are blue.

These FPGA lines are digital 0 and 1s; but the VGA monitor wants analog RGB values, so you need a DAC (digital analog converter).
The following video shows you how this can be done: https://www.youtube.com/watch?v=wzhDRIX2Ors <https://www.youtube.com/watch?v=wzhDRIX2Ors> (3:22 - 7:00)
you see that Magnus foresaw three somewhat similar resistors for RED (RED0=2000 Ohm, RED1=1000 Ohm and RED2=560 Ohm).

Now to „invert“ colors, it somewhat depends on what you expect. The easy one first: inverting white should result in black, shouldn’t it?
But what do you expect as inverted color of „orange“?

The easiest way to define „inverting colors" is to invert all bits and accept the outcome.
Hence inverting 0FF8000H (orange) results in 0007FFFH (="pure blue")

br
Jörg

> Am 18.10.2018 um 11:29 schrieb Tomas Kral <thomas.kral at email.cz>:
>
> On Tue, 16 Oct 2018 14:57:11 +0200
> Tomas Kral <thomas.kral at email.cz> wrote:
>
>> I cannot decide on the
>> palette map. In RGB triplet, leftmost byte influences RED most,
>> middle green, and last blue.
>
> Quite the opposite.
>
> Best results obtained so far, by reordering bits in RGB register.
> // RGB[7:0] = BB GGG RRR
> assign RGB = {color[23:22], color[15:13], color[7:5]};
>
> Which I believe is matching resolution of Pepino LX9 board.
>
> Colour map now appears like this.
>
> 00000000  black
> 00000080  dark red | 00FFFFFF  white - based on SW[6]
> 00008000  green
> 00008080  yellow
> 00800000  deep blue
> 00800080  magenta
> 00808000  cyan
> 00808080  grey
> 00C0C0C0  light grey
> 000000FF  red
> 0000FF00  light green
> 0000FFFF  light yellow
> 00FF0000  blue
> 00FF00FF  light violet
> 00FFFF00  light cyan
> 00FFFFFF  white
>
> In invert mode SW[7], the colours do not swap as opposite, which makes
> me wonder of bit reversal.
>
> // RGB[7:0] = RRR GGG BB
> assign RGB = {<<{color[7:5]}, <<{color[15:13]}, <<{color[23:22]}};
>
> I googled that `<<' stands in Verilog for stream operator doing bit
> reversing, if I am not mistaken and the above stands to be corrected.
> It could also be little endianness that I often confuse.
>
> I really need to read some book on Verilog and FPGA, I have PDF by
> Pong, if that is good one.
>
>
> --
> Tomas Kral <thomas.kral at email.cz>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.inf.ethz.ch/pipermail/oberon/attachments/20181018/23cedc89/attachment.html>
```