[Oberon] Updated RISC5 firmware

[Jörg]

Indeed, version control is not one of NWs strengths :-)
I lately had the idea to implement „diff" and „patch“ in Oberon.
Jörg

> Am 25.10.2018 um 07:10 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> 
> All:
> 
>  while exploring the NW website, I stepped upon the paper "RISC5 Update" dated 15.6.2018. 
> 
> www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html ---> RISC5 Update
> 
> The paper says that both the CPU and the top level Verilog were improved and updated. So I started to explore.
> 
> NW website www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html 
> 
>    RISC5Top.v is dated 14.6.2018
>    RISC5.v      is dated 31.8.2018
> 
> The official www.projectoberon.com 
> 
>    RISC5Top.v is dated 3.10.15 (OberonStation)
>    RISC5Top.v is dated 14.6.2018 (Digilent Spartan 3).
> 
> However,  RISC5Top.v is the only Verilog file on the ProjectOberon website. It is in fact a direct link to the NW version.
> 
> The other Verilog files are in the archive "Verilog Source zip". So I looked into this archive:
> 
>    RISC5Top.v is dated 22.9.2015  (in the archive)
>    RISC5.v      is dated 25.9.2015  (in the archive)
> 
> Hmm. It is not the most ideal situation that the NW website is out of synch with the ProjectOberon website, which is often referred to as an official website for this project.
> 
> Not that I want to complain. But it is good to know where is the stuff. I will now download it to my own local disk and label it as the 2018 version of the firmware. 
> 
> Wojtek
> 
> 
> 
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon