[Oberon] Updated RISC5 firmware

[Tomas Kral]

On Thu, 25 Oct 2018 09:31:09 +0200
Jörg <joerg.straube at iaeth.ch> wrote:

> Multiplier:
> One version does not use the multiplier capabilities of the FPGA,
> pure shifting and adding.

Actually there are two versions of shift-add multiply/divide.
Those described in
https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC-Arch.pdf
and these here
https://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf

But on the contrary `Multiplier.v', `Divider.v' both use methods
explained in `RISC-Arch.pdf' not those in project book
`PO.Computer.pdf'.

One method makes use of so called `double registers', the other
single product, cannot tell how they differ in cycles consumed?

product register <P>
====================

module Multiplier(
 input clk, run, u,
 output stall,
 input [31:0] x, y,
 output [63:0] z);
reg [5:0] S; // state
reg [63:0] P; // product
wire [31:0] w0;
wire [32:0] w1;
assign stall = run & ~(S == 33);
assign w0 = P[0] ? y : 0;
assign w1 = (S == 32) & u ? {P[63], P[63:32]} - {w0[31], w0} :
     {P[63], P[63:32]} + {w0[31], w0};
assign z = P;
always @ (posedge(clk)) begin
 P <= (S == 0) ? {32'b0, x} : {w1[32:0], P[31:1]};
 S <= run ? S+1 : 0;
end
endmodule


double register <B,A>
=====================

module Multiplier(
 input CLK, MUL, u,
 output stall,
 input [31:0] x, y,
 output [63:0] z);
reg [4:0] S; // state
reg [31:0] B2, A2; // high and low parts of partial product
wire [32:0] B0, B00, B01;
wire [31:0] B1, A0, A1;
assign stall = MUL & ~(S == 31);
assign B00 = (S == 0) ? 0 : {B2[31] & u, B2};
assign B01 = A0[0] ? {y[31] & u, y} : 0;
assign B0 = ((S == 31) & u) ? B00 - B01 : B00 + B01;
assign B1 = B0[32:1];
assign A0 = (S == 0) ? x : A2;
assign A1 = {B0[0], A0[31:1]};
assign z = {B1, A1};
always @ (posedge(CLK)) begin
 B2 <= B1; A2 <= A1;
 S <= MUL ? S+1 : 0;
end
endmodule


-- 
Tomas Kral <thomas.kral at email.cz>