[Oberon] PO2013 - Real time measurement

[Skulski, Wojciech]

Thomas:

  A few remarks. 

The LVTTL voltage is 3.3V, not 3.5V. 

FPGAs have "banks" of IO pins which you can power with Vcco ranging from 1.2V to 3.3V. The Vcco is defining the maximum output voltage delivered by a given bank. If Vcc0o=2.5 V (for example) then the bank can drive 2.5V and no more. 

Spartan-6 FPGAs can take up to 4.1V on any input pin regardless of Vcco. It is a peculiarity of this FPGA family and I would not take it as a rule. A typical LVTTL chip may get damaged, so better do not memorize this number. It is good to know as a curiosity and never be relied upon.

It is not voltage but rather current what damages the I/O pins. If you do not want to study this subject in depth, then insert series resistors everywhere. Use 1k series resistor on every I/O pin. It will limit the current to at most a few mA, which is below the 10 mA absolute maximum rating. The resistor will decrease the edge speed. Use low frequency clock and you should be fine. Do not exceed a MHz or so if you do not want to perform a detailed analysis. Chances are it will work.

There is much more to say on the subject of voltage compliance, but the preceding may be sufficient, so let's stop here.

Concerning twelve volts, your best bet is probably a battery if you do not plan to build your own circuits. Be careful with the wires because any battery can easily output a few amps in a burst, and this will really damage any FPGA if you do not limit the current with an appropriate resistor. 

Hope it helps.

Wojtek
________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Tomas Kral [thomas.kral at email.cz]
Sent: Thursday, March 28, 2019 6:38 AM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] PO2013 - Real time measurement

On Mon, 25 Mar 2019 21:23:01 +0000
Paul Reed <paulreed at paddedcell.com> wrote:

> Certainly not the circuit you attached in your mail.

True, I picked the other picture. I am now scratching my head over High
vs Low voltage PIC programming (default on newer PICs), reading info
in the specs and on net.

Looking at a simplified PIC prog by NW, it feeds signals from
std PC parallel port at 0..5V.

Exception `MCLR' pin, which is driven 0/5/12V, not sure this is also
applicable to newer PICs. Also not clear how to make 12V out of 5V.

Low voltage may support programming in VDD operating range i.e. 2.0 to
5.5V (PIC16F8x), and requires `RB3' be pulled down by a resistor to GND.
So one more wire in addition to High voltage mode.

Exception seems `MCLR' to do bulk erase, VDD of 4.5V to 5.5V is
required!

I can now see your point, that with a slight modification of NW original
code for PC parallel port, PIC can now be programmed through FPGA GPIO
at 3.5V signal levels.

Being rather H/W numb, cannot figure out recommended wiring, I found
this on the net, with 5V to be 3.5V for FPGA, which may be close?

Then `ICSP' (in-circuit-ser-prog), possibly also requires a suitable
connector+plug, to isolate prog mode to normal operation mode. At the expense of
`RB3' that has a dedicated function.

--
Tomas Kral <thomas.kral at email.cz>