[Oberon] ULX3S oberon

[D EMARD]

HI

Here is my ULX3S oberon port.
https://github.com/emard/oberon

I started from FleaFPGA but replaced all
vendor-specific instantiations of BRAM and video fifo
with generic verilog that "should" compile the same
at different FPGA chips (but I didn't try artix-7 or cyclone-5 yet)



On 5/13/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
> Davor:
>
>   could you please remind me where can I find the code?
>
> Thanks,
> Wojtek
> ________________________________________
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of D EMARD
> [vordah at gmail.com]
> Sent: Saturday, May 11, 2019 6:41 AM
> To: oberon at lists.inf.ethz.ch
> Subject: [Oberon] ULX3S oberon
>
> HI
>
> I'll try to answer some questions about ULX3S.
>
> Not all parts are in lola2.
>
> Yes, cache, SDRAM are in verilog, and dvi2vga video
> converter are in VHDL. That addidional code is completely
> vendor independent and should have clean and separate register
> and combinatorial logic, so I'd say, a straightforward replacement
> to lola2 should be possible without thinking of what code actually does.
>
> cache and sdram part is done by FleaFPGA/Valentin by borrowing
> from 486 emulator  project, code just appears to work for oberon
> but I don't know details about how it works.
>
> With vga2dvi I have more experience so If you need some help
> porting this to lola2 I'll try to answer of course.
>
> 64-bit color is connected and should go to DVI/HDMI monitor display
> Just I don't know how to make something color from oberon-v5 disk image,
> attached examples seem to draw only BW
>
> I'n not sure what is with sierpinski example on oberon-v5,
> middle click reports error about file missing and doesn't start it -
> is that normal?
>
> Davor
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