[Oberon] Cheap chinese FPGA board - is it usable for PO?

[Jörg]

130 KB reichen zwar fürs gesamte System (ohne Framebuffer), aber Compiler passt dann schon nicht mehr zusätzlich rein.
Fürs SDRAM-Ansteuern gibt es zwar fix-fertige OpenCores, aber die müsste erst jemand in RISC5Top integrieren.

Jörg

Am 11.11.19, 16:19 schrieb "Oberon im Auftrag von Treutwein Bernhard" <oberon-bounces at lists.inf.ethz.ch im Auftrag von Bernhard.Treutwein at Verwaltung.Uni-Muenchen.DE>:

    Hi Paul,
    
    [...]
    >
    >In general it's pretty hard to amortise the significant cost of such an effort
    >over just a reduced board price, even at very high quantity; and especially so
    >in this case, for a number of reasons which become apparent when you start
    >doing deeper research on this particular FPGA.
    >
    thanks for the warnings. 
    
    >The chip is unusual for an FPGA in that the useful memory is synchronous
    >dynamic RAM bonded onto the programmable logic inside the physical
    >package, thereby saving I/O pins which would otherwise be used to interface
    >to external memory; but again, it's DRAM, which is a lot harder to interface to
    >than the fast asynchronous static RAM in the Project Oberon 2013 edition
    >reference design.
    >
    
    the specs say that it has 130KB SRAM and in addition tot hat SDRAM
    
    >I'd be happy to discuss it further but I can't help thinking that any effort
    >someone wanted to spend would be better utilised in almost any other
    >direction... :)
    >
    quite discouraging :-(
    
    --
      Bernhard
    --
    Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
    https://lists.inf.ethz.ch/mailman/listinfo/oberon