[Oberon] Oberon on ULX3S explanation

[Skulski, Wojciech]

Peter:

  Wikipedia is not an authoritative source of info on electronic parts. I often consult Wikipedia, but it tends to be confusing. 

FYI, I used 4 MB of synchronous ZBT RAM in RiskFive design. It is an improvement over the asynchronous RAM (ASRAM) because it is both faster and it has well defined timing. IMHO it is the best kind of memory for this application. But both ASRAM and the ZBT are expensive and they both use lots of pins. Neither the ASRAM nor the ZBT are practical beyond 4 or maybe 8 MB. 

A modernized version of the Oberon System will need some 32 MB, according to some gossip in this group. Some people have System-3 in mind. Also the A2 derivative might be of interest. Both will need more than a few megabytes. Even 32 MB seems frugal. Present day technology can easily use an SDRAM for a 64 MB design, or DDR3 for 512 MB. But here we are running into those performance issues.

My own idea is a hierarchical memory with 2MB or 4 MB of fast ZBT, and all the rest being some sort of DRAM. The HyperRAM is tempting because it is easy to layout on the board with only 12 pins per 16 megabytes. In such a system The core Oberon modules can execute in the fast RAM, while the less time critical ones can be assigned to slower memories. For this scheme to work (or even to be tried) we would need a loader which can be told where to load particular pieces. In future one can also add a cache to such a board.

Thanks, 
Wojtek



________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of peter at easthope.ca [peter at easthope.ca]
Sent: Friday, November 15, 2019 1:52 PM
To: oberon at lists.inf.ethz.ch
Subject: [Oberon]  Re: Oberon on ULX3S explanation

Wojciech,

According to Wikipedia, chips up to 2 MB are available for
asynchronous and synchronous uses.
https://urldefense.proofpoint.com/v2/url?u=https-3A__en.wikipedia.org_wiki_Static-5Frandom-2Daccess-5Fmemory-23Contemporary-5FSRAM-5Fdevices&d=DwICAg&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=uUiA_zLpwaGJIlq-_BM9w1wVOuyqPwHi3XzJRa-ybV0&m=qt8ZTEeTPkHdTuB8HcpfqQvYPjkoTM65LctLwn74i8I&s=8WXQdoYtwpZrjA4GAC6B5mqzU80fVSBXSuvrQ9JfPJ4&e=
Therefore a board with 4 or 8 MB should be quite feasible.

From:   "Skulski, Wojciech" <skulski at pas.rochester.edu>
Date:   Thu, 14 Nov 2019 15:47:43 +0000
> It would be good to know the actual random access time in a
> practical system using SDRAM. The numbers which we get from the chip
> data sheets are not necessarily realized in practice. If you could
> somehow gather this info then we would have at least one data point.

This and other messages suggest, to me as naive reader, that you are
reluctant to commit to SRAM on your RiskFive; still considering SDRAM.
Therefore I wonder whether cost is a concern.  But RiskFive is a
high-end board.  Therefore unless the cost is extreme, it should be
tolerable for RiskFive.

Regards,                                   ... Lyall E.