[Oberon] FPGA RISC memory interfacing

[Skulski, Wojciech]

Paul:

  thank you for the note. I am facing a practical problem that I would like to use RISC5 and the rest of the FPGA Oberon System in practical situations. The limitation that it only works well with asynch RAM is a serious one. I wonder how easy it will be to convert RISC5 to a synchronous design.

FYI, I am not sure if the present design works well with Pepino whose idea is almost the same as the original Spartan-3 board. It is the same memory connected to Spartan-6 rather than Spartan-3. I noticed that Oberon System frequently freezes on one Pepino which we have. I have not identified any pattern. Sometimes it works for days, and sometimes if freezes after a mouse click on a command like the Hilbert curve. I suspect a timing violation. 

Reengineering the CPU may help solve this problem. 

Thank you,
Wojtek
________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Paul Reed [paulreed at paddedcell.com]
Sent: Sunday, December 22, 2019 8:56 AM
To: ETH Oberon and related systems
Subject: [Oberon] FPGA RISC memory interfacing

Hi Wojtek,

> I want to connect ... to a memory chip ... IS61NLP102418B-200B3L.
> ... A quick look at the RISC5 code reveals that the state machines seem
> not be present in this code...So this design is quite interesting.
> Most of the RISC5 code is combinational...

Right, it's not a pipelined design.

Also I think the intention is to explain its operation for a general
audience, not for an electronics designer.  Nevertheless it's pretty
clear, certainly in comparison with most other designs out there.

To see the effects of the combinational choice, you would need to do
some more realistic simulation, e.g. post-synthesis, rather than just
simulating the Verilog source, to see the effects of the actual delays
in the real hardware, which are very significant.

That ISSI synchronous memory chip would probably work better with a
pipelined design like RISC-V.  Prof. Wirth's RISC works well with
asynchronous SRAM, as has already been discussed.

HTH,
Paul
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