[Oberon] FPGA RISC memory interfacing

[Skulski, Wojciech]

Michael:

I wonder if we can add a firmware module which will monitor memory usage and interrupt the processor in case of illegal memory access. I am not sure what would be the condition to trigger such an action. 

Your "guard page" remark made me think that one possible way is to use a discontinuous memory map with separate memories for the stack and the rest. The physical memory can be continuous, but the memory map does not have to be. A firmware address translator is not hard to develop. We can manipulate the address bits any way we want. So I can imagine adding the guard pages not to the processor, but to the system in a form of a separate firmware module.

The very simple guard pages could look like this. Declare a large stack space like 1 MB, and map it to the physical stack of say 32 kB. Any access beyond the 32 kB will trigger the guard firmware to issue an interrupt. Physically the memory will be continuous (e.g., 1 MB on Pepino), but the address map known to the processor will be 1 MB for the stack and the next 1 MB for the rest. The gap within these 2 MB will be protected. 

I am sure this proposition is incomplete. Perhaps it can be developed further.

Wojtek

you said: 
> Another (less likely) cause of freezes or memory corruptions could be a
> stack overflow, which will cause the stack to overwrite parts of the
> modules space. As the RISC5 CPU does not support memory segmentation or
> guard pages, I assume this would be the hardest to fix. The only way I
> can think of is storing the stack limit at some fixed memory address and
> emitting check code by the compiler whenever the stack pointer is
> reduced, which will have a noticable runtime penalty.
> Or just be careful when doing recursion to not cause stack overflows :-)