[Oberon] QEMU target implementation for Oberon RISC architecture

[Joerg]

Hi Charles

Nice.
You must have changed some Oberon files like Fonts.Mod and Texts.Mod.
Didn’t browse through all your qemu fork yet. Are your Oberon changes available somewhere?

Jörg

> Am 28.12.2019 um 02:37 schrieb Charles Perkins <chuck at kuracali.com>:
> 
> 
> This is to let you all know about a fork of QEMU (a very fast emulator with lots of features) introducing the Oberon RISC architecture.
> 
> https://github.com/io-core/qemu-risc6
> 
> It is unfinished and I probably should have waited to announce it but the new year starts soon and I just want to share some pretty (to me) pictures.
> 
> As it says in the readme on the github page, the target is named risc6 to avoid confusion with the already existing riscv target in qemu and because in one communication (An Update of the RISC5 Implementation) Professor Wirth defines module RISC6 to introduce interrupts into the architecture. 
> 
> I intend to update the readme with build instructions and binaries that can be simply downloaded, etc.
> 
> Happy Hacking,
> Chuck
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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