[Oberon] QEMU target implementation for Oberon RISC architecture

[Jörg]

Hi

You can ask the RISC processor to reveal its version with this code

   cpu := SYSTEM.H(2019) MOD 80H;
   IF cpu = 53H THEN       (* RISC5: with interrupts + floating-point, 31.8.2018 *)
   ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)
   ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)
   END;

br
Jörg

Am 30.12.19, 09:56 schrieb "Oberon im Auftrag von Paul Reed" <oberon-bounces at lists.inf.ethz.ch im Auftrag von paulreed at paddedcell.com>:

    Hi Chuck,
    
    > ...the target is named risc6
    > to avoid confusion with the already existing riscv target in qemu and
    > because in one communication (An Update of the RISC5 Implementation
    > [1]) Professor Wirth defines module RISC6 to introduce interrupts into
    > the architecture.
    
    Sorry I think that's a mis-print since it's the only occurrence, I'm 
    pretty sure the intention was to keep it as RISC5.  Apologies for any 
    confusion.
    
    As it happens most of the stuff for interrupts was there originally 
    anyway before the update, especially in the compiler.  The RISC5 source 
    on Prof. Wirth's site definitely contains the interrupt code now.  
    There's also a RISC5a version, without interrupts and without 
    floating-point.
    
    Cheers,
    Paul
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