[Oberon] Negative integer literals in Oberon

Skulski, Wojciech skulski at pas.rochester.edu
Sun May 3 05:32:14 CEST 2020


>With 32bit INTEGERs and max 24bit address bus 
> of the RISC5 (max 16 MB) you don‘t run into 
> this overflow problem.
> SYSTEM.GET/PUT can handle „negative“ values 
> (=large positive values) correctly.

The 24 bit address bus is an artifact of this particular Verilog implementation file. 
The full address bus is 32 bit and it can easily be routed to the rest of the design 
and to the FPGA pins as well. If someone wanted to use an FPGA board 
with a large DRAM, then one can route all the bits. It would make sense after 
adding a cache to the CPU, which is a separate issue. 


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