[Oberon] Unlimited Oberon System for any board

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Skulski,
> Wojciech
> Sent: Monday, 4 May 2020 5:11 AM
> To: ETH Oberon and related systems
> Subject: [Oberon] Unlimited Oberon System for any board
> 

Wojtek,

That is an ambitious project - I wish you every success with it. My experience and enthusiasm for some of the topics you mention are quite different from yours but I don't see much to be gain by saying I like 'eating strawberries' when you say you like 'eating steak'. John Roberts drew together a whole lot of hardware-related possibilities in his post in 2016. It might be worth revisiting it:

[Oberon] Inexpensive Hardware: Cost vs Objectives

http://lists.inf.ethz.ch/pipermail/oberon/2016/008923.html

However I will comment on a number of claims that I believe are potentially misleading:

> 
> The Digilent board was discontinued (contrary to Chris saying that Digilent
> keeps their products alive for a long time). 

According to the following document, the Starter-3 board that Project Oberon 2013 was initially implemented on, was developed in 2004.

https://www.xilinx.com/support/documentation/boards_and_kits/ug130.pdf

Production was discontinued sometime in 2014. I consider 10 years to be 'a long time' for the target audience of this sort of product. With hindsight It would have been better if I had said something like 'more than 5 years' and left the reader decide whether this was a long time or not. 

> Pepino could be assembled with 2 MB, but I am not sure if it was.

I can confirm it was. I purchased a 2 MB Pepino from Saanlima in Jan 2016. 

The Pepino is not the only board I have with 2 MB of RAM. I also purchased a 1 MB Pipistrello board with an additional 1 MB of RAM on the 'Oberon Wing' daughterboard. 
> 
> In summary: All the Oberon Software is still limited by the accident which
> happened in the past, which was a particular board with a particular amount
> of SRAM. The progress is still limited this design decision taken long time
> ago.
> 

Note that there was a significant change to the RISC5 implementation in Verilog in 2018. There were some changes related to the addressing of RAM. The 'changes' file (news.txt) on Wirth's site has the following entry:

20180628 - Update of RISC5, see RISC5.Update.
  Cleanup; new feature: Interrupts. Instruction set unchanged.
  New source files: RISC5Top.v, RISC5.v, RISC5a.v, Registers.v
  (RISC5a is RISC5 without floating-point and without interrupt)

More details and the motivation for these changes are described in the document:

https://inf.ethz.ch/personal/wirth/ProjectOberon/RISC5.Update.pdf

> Recommendations:
> 
> 2. Boards with more powerful FPGAs and more memory are needed to break the 1
> MB barrier. 

There is (now) no such 1 MB barrier. See above.

> 
> 8. The RISC5c can be then used with commercial FPGA boards which tend to use
> the DDR chips these days.
> 

That would be useful. I thought that has already been done by the Radiona guys, hasn't it?

Regards,
Chris Burrows
CFB Software 
https://www.astrobe.com/RISC5