[Oberon] Unlimited Oberon System for any board

Frans-Pieter Vonck fp at vonck.nl
Fri May 8 19:31:17 CEST 2020


There is a collaborative board that is used by ETHZ and Bologna.


For me these boards with multiple processors are to complex.

I bought a hifive arduino board to play along with this Risc-v assembly 
The documentation of hifive, an offspring of the Berkeley researchers 
that made Risc-v.
Probably i will jump to the cheap nano board.
But the documentation, like withthe esp chips, might be slacking.

Frans-Pieter Vonck

Skulski, Wojciech schreef op 2020-05-08 17:19:
> Guy:
>> What about using RISC-V ISA on FPGA, allowing for “some kind of” easy 
>> path between RISC-V chips and FPGA made systems?
> Have a look at
> http://opencores.org/project,hf-risc   (older version)
> https://github.com/sjohann81/hf-risc (newer version)
> The older version from Open Cores runs on the same Spartan-3 starter
> kit which originally hosted RISC5. The newer version removed that
> support and added some other stuff. The highlights which are worth
> exploring:
> 1. The project is mostly in VHDL which I like much better than NW 
> Verilog.
> 2. The structure of the HF-RISC-V seems more clear to me than RISC5,
> which is IMHO too terse with too few comments (ETH specialty, I
> guess).
> 3. The HF CPU is explicitly pipelined and there is some discussion.
> The discussion is a little bit above my head, but at least there is
> hope of understanding.
> 4. There is also a MIPS variant in the same archive. It may be
> interesting to compare the three approaches, HF-RISC-V, MIPS, and
> RISC5.
> Please note that this is "a RISC-V" rather than "the RISC-V". I am not
> sure what is the connection between *this* RISC-V and the official
> one. I suspect that just like there is no "the ARM", there is no such
> thing as "the RISC-V" either.
> Hope it helps,
> Wojtek
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related 
> systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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