[Oberon] Project Oberon running from LPDDR memory on Pipistrello

[Jörg]

I try to fix the bug in the Oberon environment.
Jörg

Am 11.05.20, 03:23 schrieb "Oberon im Auftrag von Magnus Karlsson" <oberon-bounces at lists.inf.ethz.ch im Auftrag von magnus at saanlima.com>:

    I should clarify:
    On power-up the cache is targeting the lower 128KB of the 1MB address space.
    
    Magnus
    
    On 5/10/2020 6:12 PM, Magnus Karlsson wrote:
    > FYI, I have worked the last week with Jörg Straube on getting Project 
    > Oberon running from DRAM on the Pipistrello board and I just checked 
    > in the code on github:
    > See 
    > https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr
    >
    > It's using a 128KB cache organized as a 2-way 256-set cache with 256 
    > byte cache lines.  The interface between the cache and the memory 
    > controller is 128 bits wide @100 MHz, and the memory controller itself 
    > has 800 MB/s peak memory bandwidth.
    > On power-up the lower 128KB of the 1MB address space is covered by the 
    > cache.  The main code for the cache is a simple state machine using 
    > about 150 lines of code with 4 states.
    >
    > The cache actually covers the lower 8MB address space so in theory we 
    > could have an 8MB Oberon system, but due to a bug somewhere in the 
    > Oberon code it crashes after about 1.25 sec with a trap (C2H on the 
    > LEDs) with more than 1MB of memory.  The solution is to have the 
    > non-io address space aliased to the first 1MB.  It seems like there 
    > are memory access cycles above 1MB that needs to actually affect the 
    > memory at the first 1MB.  I did discover this way back when I did the 
    > 2MB version of Pepino and had the tie address bit 20 to 0 for it to 
    > boot (i.e. alias the second MB to the first MB) but never got around 
    > to pinpoint the problem.  The same problem popped up again and I was 
    > able to trace it down.
    >
    > Video memory is in dual-port BRAM and can be relocated by writing to a 
    > new register.  At power-up the video is a the normal spot (0E7F00H) 
    > but can be moved up above the 8MB boundary to have a continuous 8MB 
    > memory section for program and data by simply writing to a register 
    > with the new video base address.
    >
    > Cheers,
    > Magnus
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