[Oberon] HDMI question

[Skulski, Wojciech]

Well, the proof of the pudding is in the eating. If it works then your design must be OK.

On the other hand, I tend to follow what the data sheets are saying. So in the Spartan-6 user guide UG381 (v1.6) February 14, 2014 there is schematics, showing the 50 ohm resistors to Vcc=3.3V at the far end of the cable. There are no caps shown on that page, which is important because if the caps are needed then Xilinx will tell you so. 

Wikipedia says that DC coupling is part of the specs: 
https://en.wikipedia.org/wiki/Transition-minimized_differential_signaling

The physical layer for TMDS is current mode logic (CML),[2] DC coupled and terminated to 3.3 Volts. While the data is DC balanced (by the encoding algorithm), the DC coupling is part of the specification. TMDS can be switched or repeated by any method applicable to CML signals. However, if DC coupling to the transmitter is not preserved, some transmitters' "monitor detection" features may not work properly. 

>From all this I take home that I better insert the TMDS repeater TMDS141RHAR in the signal path to protect the FPGA. The downside is that Guy will need to solder the QFN package to his board. It will be fun. I assembled a ton of these in the past and it always worked. So it can be done.

Thank you,
Wojtek


________________________________________
From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of D EMARD [vordah at gmail.com]
Sent: Sunday, May 17, 2020 5:26 PM
To: ETH Oberon and related systems
Subject: Re: [Oberon] HDMI question

Our 1st prototype had no C and directly to the pins.
One board outputs are fried during plugging of connector without GND on shiled
board still works no video anymore. So the C came and no further
boards are fried.

ULX3S has been tested to drive 30-m overhead projector so I'm pretty
shure it's well done.

Caps represent 0-ohm AC impedance so the impedance will be the same
with or without caps but it doesn't matter.

I'm not further expert in electrical standarts but my guess is that TMDS is
current mode differential, not voltage mode like LVDS so final termination in
monitor may be 0ohm (theoretically)


On 5/17/20, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
> D.Emard:
>> Signals are DC balanced so if you want to do only output
>> to monitor, just use C in series to every TMDS wire
>> value doesn't matter some boards use 100nF  I use 220nF
>
> On a further thought, this may be problematic. TMDS needs to be DC
> terminated with 50 ohms to 3.3V. If you insert the cap then DC termination
> needs to be before the cap, which is on your board. Then the monitor will
> provide its own termination, again with 50 ohms to 3.3V. It means that you
> are driving two terminations in parallel, which is 25 ohms. It is out of
> TMDS specs according to the data sheet. The FPGA may be able to pack enough
> current and reach the prescribed swing, or it will keep the current and the
> voltage will get reduced by two. It probably depends on the details of the
> driver which are hard to guess outside the specs.
>
> My conclusion is that I either provide the HDMI connector w/o any caps or I
> provide the redriver chip. Not sure yet. I will look how much space I still
> have on the board.
>
> Thank you,
> Wojtek
>
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