[Oberon] Project Oberon, RISC-V Edition

[Andreas Pirklbauer]

For those of you who have followed the RISC-V project over at UCB
over the past decade or so, the plot now thickens, e.g.

https://arstechnica.com/gadgets/2020/12/new-risc-v-cpu-claims-recordbreaking-performance-per-watt/

It is now generally believed that RISC-V will find its way into more and
more “real" use cases over time, and could eventually even become a
threat to the mainstream processors. But this will take many years, but
the sheer number of companies  in the Valley currently entering this
space indicates that it may happen sooner rather than later. At least
in some specialized areas.

In any case, apart from what is happening “in the mainstream”, I now believe
that RISC-V  may end up being one of the few truly interesting target ISAs
for to pursue for Oberon as well (think: "Project Oberon, RISC-V Edition”).

An experimental single-pass Oberon/Oberon-2 compiler backend (i.e.
module OVG) already exists (well, at least for RV32I and RV64I and
some of the already ratified extensions).

Now we only need a simple target board as a suitable target. Anyone
interested in replicating what has been done for the RISC5 FPGA HW?

-ap