[Oberon] Re: Documentation;

[peter at easthope.ca]

From:	Andreas Pirklbauer <andreas_pirklbauer at yahoo.com>
Date:	Mon, 18 Nov 2019 21:04:32 +0100
> the compiler generates the instruction 
> | BL (4) | cond (4) | mno (4) | pno (8) | pc-fixorgP (12) |,

Referring to "The RISC Architecture" available from NW's site 
and mirrored by PR.
http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC-Arch.pdf
http://www.projectoberon.net/wirth/FPGA-relatedWork/RISC-Arch.pdf

Section "1. Register instructions" mentions "... extended to 32 bits 
with 16 v-bits to the left." What is a v-bit?

Andreas' instruction is similar to the branch instruction on page 2.
The only interpretation I've imagined for BL is Branch Less.
That's LT; not LS, not LE?

mno = module number
pno = program number

Beyond that I can't match the stated instruction to the template on page 2.

Clarification or hint welcome.

> ... which the module loader then fixes up ...

My recollection of fixup is just a shift in frame of reference. 
Offset in memory = (offset of module) + (offset in module)

> ... (here, a simple visual would probably help) and, perhaps, point the 
> reader to the relevant pieces of code in ORG.Call and Modules.Load.

Will think about that after I understand the branch instruction.

Thanks,                             ... L.


-- 
Tel: +1 604 670 0140            Bcc: peter at easthope. ca