[Oberon] Re (n): RISC5 Verilog

[peter at easthope.ca]

From:	Paul Reed <paulreed at paddedcell.com>
Date:	Sat, 19 Dec 2020 11:36:32 +0000
> It is a conscious choice to avoid an assembler syntax and formal 
> mnemonics for RISC5. In the preface to the FPGA version of Project 
> Oberon, Prof. Wirth writes ...

Thanks Paul.  I didn't intend criticism.

The old Intel _386^TM_DX_Microprocessor_Programmer's_Reference_Manual_ 
here, which I've never used, has similar notation.  When a student, I 
happened to miss the assembler course.  The style of notation must be 
entirely straightforward for professionals.

Probably the one advantage an outsider has is taking almost nothing 
for granted.

Thanks again,                   ... P. L.

-- 
Tel: +1 604 670 0140            Bcc: peter at easthope. ca