[Oberon] RISC5 Architecture

[Hellwig Geisse]

Dear all,

I want to open just another can of worms... ;-)

Do we have a common dependable definition of the standard hardware
the Oberon software is expected to run on? I think that the defining
document should be "The RISC Architecture" [1], which bears the date
"NW 5.12.10, rev. 9.8.2018". This is the latest document on RISC5
I'm aware of. I think that this paper does not answer the following
questions (please note that I myself guessed answers while writing
my RISC5 simulator, but I was never sure to have guessed right):

1. What is the endianness of RISC5?
2. Is the offset in memory instructions (format F2) sign-extended?
3. The SUB instruction "also sets the C flag". How is this to be
   interpreted? Example: compute 3-5. If you really subtract in
   binary, the carry will be set. If you add -5 in 2's complement
   representation, the carry will be cleared.
4. What happens on (synchronous) exceptions?
   a) unaligned word access
   b) unknown instruction
   c) division by zero
   d) floating-point overflow
   e) floating-point underflow
5. What happens exactly on interrupt?
6. Are nested interrupts supported?
7. Does STI delay the setting of intenb by one instruction?
   Does RTI automatically set intenb?
   If both questions are answered negatively, then there is
   a race condition in the sequence (STI, RTI), with a nested
   interrupt as a possible result.
8. Can external devices other than the timer interrupt?
9. All external devices are grossly underspecified.
(The list is not complete.)

Although I really want these questions to be answered, what
interests me most is: *how* do we find answers to them?
Some alternatives are:
 - Anything that is not specified is intentionally left so.
   Implement at your free choice. This will severely hamper
   exchanging software, especially in binary form.
 - Take NW's implementation and analyze the circuits (or
   just try it out). This promotes his implementation to
   a "reference design".
 - Choose any one of the various simulators and declare it
   to be the "gold standard". Which one?
 - Discuss each question here on the list and come to
   an agreement. A bit cumbersome, but manageable.
Other ideas?

Thanks,
Hellwig

[1] https://people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC-Arch.pdf