[Oberon] Re (2): Emulating interrupts in oberon-risc-emu as in the RISC5 specification

peter at easthope.ca peter at easthope.ca
Wed Mar 31 16:01:48 CEST 2021

>From Charles Perkins, Tue Mar 30 23:45:07 CEST 2021 
> I wanted to explore interrupt handling in Oberon ...

LDPSR is now in the glossary.

Review can be helpful.  Feedback is welcome, here or in a private 
message.  Or edit directly.  (It's a wiki.)

Regards,                         ... P.

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