[Oberon] Accessibility of FPGA configuration to V5 system.
schierlm at gmx.de
Sat Jul 24 15:21:45 CEST 2021
Am 24.07.2021 um 05:57 schrieb peter at easthope.ca:
> Can the V5 system ascertain the configuration of the host FPGA?
> Can the V5 system change the configuration of the host FPGA?
The V5 system treats the RISC5 processor as a black box. It is not aware
whether it is implemented as FPGA, as an ASIC or an emulator.
While there is LOLA, it will only output Verilog and there are no tools
in V5 to compile these to a bitstream of any FPGA model.
Also, the processor does not expose any way of altering (parts of) the
bitstream it is running from.
I hope that answers your questions.
More information about the Oberon