[Oberon] Emulators / Hardware Enumerator

Michael Schierl schierlm at gmx.de
Sat Feb 12 21:31:38 CET 2022

Hello Hellwig,

Am 08.02.2022 um 11:58 schrieb Hellwig Geisse:

> Cache flush/invalidate instructions are part of the instruction
> set of ECO32. We made them accessible from Oberon through the
> SYSTEM module. E.g., in KERNEL.MOD you find the statement
> "SYSTEM.CCTL(7)" which does the combined D-cache flush and
> I-cache invalidate needed after loading a module.

Can you think of any other memory or caching related functionality that
a generic Oberon distribution would need?

It occurred to me that having to explicitly flush instruction caches
would also help authors of emulators that do just-in-time instruction
translation (to decide when to invalidate such translations).

To help both use cases, I would add this to the hardware enumerator

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### `ICIv`: Instruction cache invalidation

When present, the CPU has an instruction cache that is not automatically
invalidated when memory (or data cache) is written to. Therefore, before
newly written code can be executed, the instruction cache needs to be
invalidated (and any data cache flushed) by writing a `0` to a MMIO
address. This can also be used by emulators that do just-in-time
instruction translation to efficiently flush their translated instructions.

In case a value other than `0` is written to the MMIO address, the
hardware may also flush all its instruction cache. Or (if feasible) it
can only flush those instructions whose memory address is greater or
equal than the written value.

Values of the `ICIv` descriptor:
- MMIO address

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