[Oberon] Compiler Construction on projectoberon.net

[Chris Burrows]

On Sun, Mar 27, 2022 at 9:38 PM John Stout <cuspcomputers at gmail.com> wrote:

> Hello everyone
>
> I'm working on a compiler and emulation of the RISC processor detailed in
> the latest (?) edition of Compiler Construction by Professor Wirth from CompilerConstruction1.pdf
> (projectoberon.net)
> <http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf>
> .
>
> I can't follow the Oberon code for the emulator in section 9.5 in the
> section handling memory instructions, which differs from Peter De Wachter's
> Oberon RISC emulator at https://github.com/pdewacht/oberon-risc-emu.git
>
> In Compiler Construction, once an instruction has been decoded as a memory
> instruction the address is calculated using
>
> adr := (R[b] + IR MOD 100000H) DIV 4;
>
> which (apart from the DIV 4) agrees with the code in oberon-risc-emu
> (which also sign extends the offset before adding it).
>
> If adr >= 0 then a load is carried out, and the N and Z flags set
> depending on the value loaded.
> However (and this is the bit I don't understand) if adr < 0 then a store
> is carried out, whereas in oberon-risc-emu u bit of the instruction is
> checked and if 0 a load is carried out and if 1 a store is carried out.
>
> Since I know oberon-risc-emu works, and that agrees with the settings for
> the u and v bits in Compiler Construction then I assume that must be the
> correct implementation, but is there an error in Compiler Construction or
> am I missing something very simple?
>
> All the best.
>
> John Stout
>

Have a closer look. In Compiler Construction the test for load / store is
NOT based on the sign of adr, it is based on one of the following
equivalent tests:

IF ~ODD(IR DIV 20000000H)  (* in the book *)

or

IF ~ODD(ASH(IR, -29)) (* in the accompanying source code *)

--
Regards,
Chris Burrows
CFB Software
https://www.astrobe.com/RISC5
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