[Oberon] ALU 2015 and 2018

Magnus Karlsson magnus at saanlima.com
Tue May 10 17:21:47 CEST 2022


On 5/10/2022 2:40 AM, Hellwig Geisse wrote:

> NW's design is a two-stage pipeline, as he explains in his documents (at least
> indirectly: "In the first cycle the address is computed and the data are fetched
> or stored. In the second cycle, the next instruction is fetched"). It exhibits
> rather long delays indeed, and could possibly be sped up by dividing the pipeline
> into more stages. I once thought about doing that, but then one would want to
> integrate caches too.

The RISC5 cpu is non-pipelined -normally each instruction takes one 
clock cycle to complete, and in the same cycle the next instruction is 
fetched.  One exception is if the instruction is a LD or ST.   In that 
case the memory access slot is used by the instruction so the next 
instruction fetch is pushed out to the next cycle, causing the cpu to 
stall for one cycle. Other exceptions are instructions like MUL and DIV 
that takes several clock cycles to complete.


More information about the Oberon mailing list