[Oberon] ALU 2015 and 2018

Skulski, Wojciech skulski at pas.rochester.edu
Wed May 11 20:25:58 CEST 2022

> I agree that this old Verilog code [I removed the code -- ws]
> looks nicer than this new one
> The new one has a shorter max latency! Eg in the old code decoding DIV 
> passed thru 11 multiplexers. In the new one passing through 4 multiplexers 
> is enough for all instructions.
> Sequential vs binary search.

Is there a way to write efficient code in Verilog that would also be readable? If not then why not? 

According to ISE help, the ternary assignment is meant as a 2-to-1 multiplexer. Replacing <input> with another such instruction is a sort of abuse of the human reader. I wonder if the same effect can be achieved with the more readable if-then-else which is meant for the human eyes rather than compiler's. 

assign <output_wire> = <1-bit_select> ? <input1> : <input0>;

Any thoughts on this?


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