[Oberon] ALU 2015 and 2018

[Hellwig Geisse]

All,

in order to bring this thread to a reasonable end, I did a bit
more work on the simulation of NW's original RISC5 design:

1. The PROM is now "pluggable". You can choose one of the PROMs
in fpga-RISC5/v0/proms and copy it over fpga-RISC5/v0/prom.mem,
which then (in the next run of the simulator) is used as PROM.

2. I added a rather coarse simulation of SRAM to the description,
which works correctly when driven by the original RISC5 circuit.
Having that implemented, I programmed a second PROM, which copies
instructions into the RAM, and executes the same program as in
the first PROM, but now with the instructions coming from RAM.
I took screenshots from both runs (and put them in the v0/proms
directory too). You can see that the behavior does not change,
no matter from where the program is executed.

3. I added two signals from VID.v to the signal display, "req"
and "vidadr", so that the interaction of the video circuit with
RAM access from the CPU can be inspected.

Thanks for the discussion.

Hellwig