[Oberon] Emulating Project Oberon's RISC5 Architecture using Icarus Verilog

[Elen Edain]

Hello and Greetings from Iceland,

I am currently undertaking a project to simulate the Project Oberon RISC5 system architecture using Icarus Verilog, aiming to replicate the system’s environment in a manner similar to QEMU for educational exploration. This endeavor is inspired by Niklaus Wirth's educational vision, focusing on understanding system design comprehensively.

Despite progress, I've encountered a challenge with emulating specific FPGA modules (originally on a Digilent Spartan 3 board), notably the DCM, RAM16X1D, and IOBUF modules, as a software simulation. This aspect falls beyond my expertise as a software engineer, primarily dealing with hardware emulation nuances. Thus I am on a learning journey as well and it is early days.

I am seeking the community's expertise and advice on simulating these FPGA modules in Verilog, to further develop a detailed tutorial aligned with Wirth's original documentation, thereby eliminating the dependency on the original FPGA board.

The ultimate aim is to produce a contemporary, step-by-step guide for working through the Project Oberon ecosystem without the need for the original FPGA board. Any advice, resources, or guidance on where to start with these hardware component emulations would be greatly appreciated.

Best regards,

Elen
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