[Oberon] The 2013 Project Oberon System running on RISC-Vinstead of RISC-5

[Michael Engel]

> On 5. Aug 2026, at 20:32, Rochus Keller <me at rochus-keller.ch> wrote:
> 
> @ Michael Engel
> 
> Cool, thanks for the hint. From the very brief description in the readme I have the impression
> that it was mostly Peter De Wachter's RISC-5 emulator run on RISC-V. Is there a
> more detailed description available somewhere?

Rikke's project report is included in the repository: https://github.com/solbjorg/oberon-riscv/blob/master/report.pdf

What Rikke did is to modify Peter De Wachter's emulator to emulate a RV32IM CPU (ultimately based on Ted Fried's RV32 emulation code at https://github.com/MicroCoreLabs/Projects/blob/master/RISCV_C_Version/C_Version/riscv.c) instead of Niklaus Wirth's RISC5 and then integrate and adapt Samuel Falvo's RISC-V Oberon compiler from Project Norebo (https://github.com/sam-falvo/project-norebo/tree/master/OberonRV). 

So this is a Project Oberon system running natively on RV32IM (though in emulation) including the compiler. The one thing we did not achieve due to a lack of time is to also build an RV32-based FPGA system to run Oberon. This is still on my todo list...

Best,
    Michael