[Oberon] The 2013 Project Oberon System running on RISC-V instead of RISC-5

[Michael Engel]

@ Rochus

Thanks for summarizing the differences, it's interesting to see the distinct approaches – I definitely have to try your port!

Another interesting platform for Oberon on RISC-V might be Andrew "bunny" Huang's Baochip, an open source RV32
SoC running at 350 MHz (with an sv32 MMU!) with 4 MiB of non-volatile ReRAM and 2 MiB of SRAM. In addition, the
chip features four additional 700 MHz RV32 cores which can be used to implement peripheral interfaces and protocols
in software, somewhat like a very much extended version of the Raspberry Pi Pico's PIO programmable state machines
(this could be used to enable VGA output, PS/2 input and ideally some form of network).
I just received two of the boards: https://www.baochip.com/

The whole SoC design is open hardware, so with Oberon one could build a complete open source system. I think this
comes close to Niklaus Wirth's original ideas for his RISC5 system in Project Oberon 2013. I'm very much tempted to 
try to port Rikke's system to the Baochip in my upcoming vacation... 

Working with Rikke on her Oberon project was a fun and sometimes pretty crazy; it was great to discuss Rikke's progress 
and ideas, often for hours each week (though unfortunately mostly online due to Covid back then).

Rikke also used her RISC-V port and knowledge to improve the system even further. We were wondering what the
minimum amount of memory would be that allowed to run the Oberon system with compiler and GUI. For this, Rikke
took an old idea, memory overlays, and adapted it to work with Oberon.

This code is also online at https://github.com/solbjorg/oberon-riscv-overlays
and Rikke's thesis is available from https://nva.sikt.no/registration/0198eaa55f73-810e68fe-af02-45b4-813b-90c006bc0603

Best,
    Michael


> On 5. Aug 2026, at 22:58, Rochus Keller <me at rochus-keller.ch> wrote:
> 
> @ Michael Engel
> 
> Thank you very much for the thesis PDF. I had a look at it and it was indeed an amazing project
> (as a student I would have loved a term assignment like that). Even though the visible outcomes look similar,
> there are significant differences in methods and results. Some examples:
> 
> - Rikke used Wirth's OR compiler running in the Oberon System and retargeted it to RV32IM; in contrast I used
>  my refactored/extended OP2 version which I transpiled to C, thus avoiding the bootstrap problem; there is currently
>  no compiler in the system and everything is statically linked, but I assume that integrating OP2 with the 
>  Project Oberon System would be not much work.
> - Rikke kept the source code as Oberon 07 while I migrated the code to Oberon 90, which was not much work and
>  allowed me to use OP2 instead of depending on the OR compiler.
> - Rikke started with de Wachter’s Oberon emulator and replaced the CPU emulation, whereas I started with a
>  generic RV32 emulator and added a thin layer to make it look and behave like Wirth's machine.
> - I avoided a hard part Rikke had to solve: Oberon’s dynamic module loader. Instead I link the whole system
>  statically and just added a few redirect procedures to the Kernel to meet the sysfixes expected by OP2.
> 
> So essentially, Rikke made the 2013 Oberon System natively self-hosting on RISC-V, while my focus was
> more on the original machine interface and reusing my external cross-build toolchain. I see it as an intermediate
> step to eventually run System 3 on the ESP32-P4 (and with some more processing steps as a
> proof-of-concept for my forthcoming Micron language and toolchain). 
> 
> In any case it was fun to read the thesis and compare the approaches, thanks again for the hint.
> 
> Best regards
> Rochus Keller
> 
> _______________________________
> From: Michael Engel
> Sent on: Wed, 05 Aug 2026 20:40:43 +0200
> To: ETH Oberon and related systems
> Cc: 
> Subject: Re: [Oberon] The 2013 Project Oberon System running onRISC-Vinstead of RISC-5
> 
> 
> Rikke's project report is included in the repository: https://github.com/solbjorg/oberon-riscv/blob/master/report.pdf
> 
> What Rikke did is to modify Peter De Wachter's emulator to emulate a RV32IM CPU (ultimately based on Ted Fried's RV32 emulation code at https://github.com/MicroCoreLabs/Projects/blob/master/RISCV_C_Version/C_Version/riscv.c) instead of Niklaus Wirth's RISC5 and then integrate and adapt Samuel Falvo's RISC-V Oberon compiler from Project Norebo (https://github.com/sam-falvo/project-norebo/tree/master/OberonRV). 
> 
> So this is a Project Oberon system running natively on RV32IM (though in emulation) including the compiler. The one thing we did not achieve due to a lack of time is to also build an RV32-based FPGA system to run Oberon. This is still on my todo list...
> 
> Best,
>    Michael
> 
> 
> 
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