<div dir="ltr">Verilog files from here <a href="http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/index.html">http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/index.html</a> is about earlier RISC version. New language report (<a href="http://www.inf.ethz.ch/personal/wirth/Oberon/Oberon07.Report.pdf">http://www.inf.ethz.ch/personal/wirth/Oberon/Oberon07.Report.pdf</a>) not about the same language as Project Oberon.<div>
<br></div><div>Also there is no common Verilog project about how all modules are connected. So right we can't reproduce Ceres-4 (from Project Oberon 2013) on FPGA.</div><div><br></div><div>PS. LONGREAL also just alias for REAL type in PO2013 compiler, also there are undocumented embedded procedures (LED procedure for example): <a href="https://github.com/ilovb/ProjectOberon2013/blob/master/ORBX.Mod#L389">https://github.com/ilovb/ProjectOberon2013/blob/master/ORBX.Mod#L389</a></div>
<div><br></div><div>Thanks, Alexey<br><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Dec 20, 2013 at 5:42 PM, Chris Burrows <span dir="ltr"><<a href="mailto:chris@cfbsoftware.com" target="_blank">chris@cfbsoftware.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Yes - it is still a 'work in progress' but the Language Report, CPU<br>
description and Verilog sources are currently on the other pages of Wirth's<br>
website:<br>
<br>
<a href="http://www.inf.ethz.ch/personal/wirth/" target="_blank">http://www.inf.ethz.ch/personal/wirth/</a><br>
<br>
There is also an updated version of Compiler Construction book.<br>
<br>
LONGINT is just an alias for INTEGER and the complete CASE statement is on<br>
its way,<br>
<br>
A version of Astrobe that supports the FPGA compiler is well underway ...<br>
<br>
Regards,<br>
Chris<br>
<br>
Chris Burrows<br>
CFB Software<br>
<a href="http://www.astrobe.com" target="_blank">http://www.astrobe.com</a><br>
<br>
<br>
From: Alexey Veselovsky [mailto:<a href="mailto:alexey.veselovsky@gmail.com">alexey.veselovsky@gmail.com</a>]<br>
Sent: Friday, 20 December 2013 10:30 PM<br>
To: ETH Oberon and related systems<br>
Subject: Re: [Oberon] Project Oberon: New Edition<br>
<div class="im"><br>
I think that Project Oberon rev 2013 not complete yet.<br>
<br>
For example Annex A1 and Annex A2 (language report and CPU<br>
description) still not published. Also there are no Verilog sources.<br>
<br>
<br>
<br>
RISC emulator module still written in Oberon rev 1990 (old CASE semantic<br>
detected).<br>
<br>
Whole system and compiler are written in strange language - it is not Oberon<br>
1990 nor Oberon rev 2013 (LONGINT and other types that has disappeared in<br>
Oberon 07/13, but new semantic for CASE that not described even in Oberon<br>
rev 2013 report).<br>
<br>
Also there are some typos, for example in 17.2.4: "From a 15 MHz clock rate<br>
results a refresh rate of 53.5 frames/s" should be replaced to "From a 25<br>
MHz clock rate results a refresh rate of 53.5 frames/s".<br>
<br>
Also I can't found description for clk25 in XGA Verilog module (what<br>
difference from clk?).<br>
<br>
We discuss Project Oberon 2013 here (in Russian)<br>
: <a href="http://oberspace.dyndns.org/index.php/topic,597.0.html" target="_blank">http://oberspace.dyndns.org/index.php/topic,597.0.html</a><br>
<br>
Thanks, Alexey.<br>
<br>
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