<div dir="ltr">The bitcoin miners used Spartan 6 units, and they are being abandoned now that ASICs are available. I wonder if these would be useful?<div><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">
On Sun, Mar 2, 2014 at 4:20 AM, greim <span dir="ltr"><<a href="mailto:greim@schleibinger.com" target="_blank">greim@schleibinger.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Some news from my FPGA Oberon board:<br>
<br>
Yesterday i was also able to compile the Verilog code from the source to<br>
the Bit-File. That was a big progress for me.<br>
<br>
I really hope that several hundreds will follow up! Also guys who are<br>
more professional then i am.<br>
I thinks this Project Oberon, or i prefer FPGA Oberon is a real great<br>
and also NEW system!<br>
If we you are thinking about the success of Arduinio and Rasberry PI<br>
which are much less innovative, then i am not so pessimistic about the<br>
future of Oberon.<br>
Maybe the fathers of the project should communicate this to Xilinx or<br>
maybe Altera . I could imagine that a Oberondinio or a Garnetberry OB<br>
;-) would be a realistic thing.<br>
<br>
As first small project and proof of concept, i personally like to<br>
realize a kind of oscilloscope.<br>
This requires:<br>
- in Verilog: the ADC converter handling and a ring buffer, with some<br>
trigger mechanism.<br>
- in Oberon: line graphic and a small user interface for showing the<br>
signals.<br>
<br>
<br>
> Still; compare the readabilty of the code of the rs232 driver written in<br>
> verilog with one written in vhdl<br>
><br>
> verilog<br>
> <a href="http://www.inf.ethz.ch/personal/wirth/ProjectOberon/SourcesVerilog/RS232R.v" target="_blank">http://www.inf.ethz.ch/personal/wirth/ProjectOberon/SourcesVerilog/RS232R.v</a><br>
><br>
> VHDL<br>
> <a href="http://opencores.org/websvn,filedetails?repname=rs232_interface&path=%2Frs232_interface%2Ftrunk%2Fuart.vhd" target="_blank">http://opencores.org/websvn,filedetails?repname=rs232_interface&path=%2Frs232_interface%2Ftrunk%2Fuart.vhd</a><br>
><br>
> Greets and happy coding,<br>
> F.P.<br>
><br>
><br>
mmm, if VHDL or Verilog in principle is better readable i can't evaluate<br>
in details. Both languages are hard to understand, at least for me, and<br>
VHDL for me is still more abstract then Verilog.<br>
<br>
One general thing is, that the Verilog code as well as the Oberon code<br>
of ProjectOberon is "poor of comments" as everybody can see at your RS<br>
232 examples.<br>
I know that Nicklaus Wirth says: "the code must explain itself", and<br>
also the book is explaining many things very well, but at some corners,<br>
some comments would be sometimes very helpful...<br>
<br>
Markus<br>
<br>
<br>
<br>
--<br>
<a href="mailto:Oberon@lists.inf.ethz.ch">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems<br>
<a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><font face="'times new roman', serif">Aubrey McIntosh, Ph.D.<br>211 E. 5th St.<br>Morris MN 56267</font><div><div><span style="line-height:20px;background-color:rgb(255,255,255)"><font face="'times new roman', serif">(512)-348-7401</font></span></div>
</div><div><div><br></div></div>
</div>