<div dir="ltr">Hi All,<div> what about this one: <a href="http://www.86duino.com/?page_id=11">http://www.86duino.com/?page_id=11</a> ?</div><div> </div><div> </div><div> There is a whole family of SoCs based on the x86 architecture :</div><div> <a href="http://www.vortex86.com/">http://www.vortex86.com/</a></div><div> </div><div>Cheers,</div><div> Darek</div></div><div class="gmail_extra"><br><div class="gmail_quote">On 2 November 2014 18:30, Peter Matthias <span dir="ltr"><<a href="mailto:PeterMatthias@web.de" target="_blank">PeterMatthias@web.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
Am 02.11.2014 um 15:40 schrieb <a href="mailto:skulski@pas.rochester.edu">skulski@pas.rochester.edu</a>:<br>
<span class="">>> A MIPS core that runs on the same Digilent Spartan 3 Starter board used<br>
>> >for RISC5 Project Oberon is available: [Plasma CPU on Open Cores].<br>
>> ><br>
>> >It is stated to be a "clean room" implementation. In the "Avoiding<br>
>> >limitations" section it does refer to operations that were the subject of<br>
>> >a 1986 patent.<br>
> They say that the patent expired in 2006. This is good. Now, who is going<br>
> to take care of the OP2 compiler for this soft CPU?<br>
<br>
</span>OP2 for MIPS still exists in source code. But Bootloader, Module loader<br>
and Decoder obviously not. At the time, the Compiler and the MIPS port<br>
were quite well and MIPS seems to have been much more upword compatible<br>
than ARM. I can not promise any output, but I can say that I want to run<br>
Oberon on my MIPS machine. More info at<br>
<a href="http://matthias.dnsdynamic.com/oberon/doku.php" target="_blank">http://matthias.dnsdynamic.com/oberon/doku.php</a><br>
<span class="HOEnZb"><font color="#888888"><br>
Peter<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
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</div></div></blockquote></div><br></div>