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</o:shapelayout></xml><![endif]--></head><body lang=DE-CH link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><font size=2 face="Trebuchet MS"><span lang=EN-US style='font-size:11.0pt;font-family:"Trebuchet MS","sans-serif"'>Hi Davide<o:p></o:p></span></font></p><p class=MsoNormal><font size=2 face="Trebuchet MS"><span lang=EN-US style='font-size:11.0pt;font-family:"Trebuchet MS","sans-serif"'>The RISC5 is clocked at 25 MHz. Because the VGA driver “steals” some time, the RISC5 effectively runs at ~23.25 MHz.<o:p></o:p></span></font></p><p class=MsoNormal><font size=2 face="Trebuchet MS"><span lang=EN-US style='font-size:11.0pt;font-family:"Trebuchet MS","sans-serif"'>Jörg<o:p></o:p></span></font></p><p class=MsoNormal><font size=2 face="Trebuchet MS"><span lang=EN-US style='font-size:11.0pt;font-family:"Trebuchet MS","sans-serif"'><o:p> </o:p></span></font></p><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><font size=2 face=Tahoma><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif";font-weight:bold'>From:</span></font></b><font size=2 face=Tahoma><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Davide Della Casa [mailto:davidedc@gmail.com] <br><b><span style='font-weight:bold'>Sent:</span></b> Montag, 18. Mai 2015 20:35<br><b><span style='font-weight:bold'>To:</span></b> oberon@lists.inf.ethz.ch<br><b><span style='font-weight:bold'>Subject:</span></b> [Oberon] Oberon on FPGA - how much does the system "stallx"?<o:p></o:p></span></font></p></div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p><div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Hi,<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>I'm reading on how Oberon of FPGA manages video generation - the chosen way is to have SRAM in common between CPU and video system.<o:p></o:p></span></font></p><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>So (reading the docs) the "stallx" line is used to arbitrate: "The signal (wire) dspreq stalls the processor (stallX) and decides whether the memory address (SRAdr) should be taken from the processor (adr) or the display controller (vidadr)".<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Now I'm wondering what percentage of time does the CPU stall because of this? Is the CPU only effectively free to work during the "invisible lines" and "beam reset" times? Or is there significant time available while "racing the beam"?<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Also I'm curious to know whether alternate solutions could potentially be in the cards to avoid the contention<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>a) dual port SRAM (too expensive / too many pins needed?)<o:p></o:p></span></font></p></div><div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>b) SRAM used in two "blocks" - one dedicated to screen and other so contention is reduced (too many pins needed?) - potentially with a way for the CPU to know if the "video" block is available.<o:p></o:p></span></font></p></div></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>c) ...?<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>(I'd think that such considerations could be worthy of inclusion in the docs by the way)<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Any links welcome about other typical arrangements of interest that are found in fpga projects "in the wild" in respect to video management...<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'><o:p> </o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Cheers,<o:p></o:p></span></font></p></div><div><p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:12.0pt'>Davide Della Casa<o:p></o:p></span></font></p></div></div></div></body></html>