[Oberon] FPGA Oberon: how is it done...

Frans-Pieter Vonck fp at vonck.nl
Fri Feb 28 21:31:13 CET 2014

Wow congratulations,
that is really fascinating.

In the evulotion of Wirth and Reeds work: logic building
blocks->alu->risc->compiler->,oberon system->peripherals: I'm still
playing with the blocks.

I just was working myself through some VHDL tutorials and I came across a
VHDL implimention for the GCD-algorithm.
This clarifies the problem of representing while loops  in logic hardware.
'While' -can be constructed with datapaths and controlunits.
I did not go through Wirth's work where the design of the while
instruction in hardware is mentioned. maybe someone can give me a hint.

Still; compare the readabilty of the code of the rs232 driver written in
verilog with one written in vhdl



Greets and happy coding,

> Hi,
> at
> a small picture
> http://www.schleibinger.com/bilder/oberon.jpg
> ProjectOberon really works!
> The SD card is written with 1K block size.
> Its now running from the Verilog and SD image files.
> I was not able to compile the Verilog files yet, still problems with
> Prom.v. I will try further...
> But many thanks to Prof. Wirth and Paul Reed for their real great work!!
> Markus Greim
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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