[Oberon] FPGA Oberon: how is it done...

Jörg joerg.straube at iaeth.ch
Mon Mar 3 14:31:38 CET 2014


>Still; compare the readabilty of the code of the rs232 driver written in
>verilog with one written in vhdl

Please find the description of the RS232 algorithm here (chapter 17.2.5,
page 20)

Perhaps the Verilog gets more obvious if you read the description (what
"midtick" does, what "run" is meant for...)


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