[Oberon] FPGA Oberon some news and a reply to F.P.

Jörg joerg.straube at iaeth.ch
Wed Mar 5 16:14:59 CET 2014


You are right the 6502 was a RISC processor. The chips evolved to CISC (most
probably an error) and tend to return to RISC now (okay, nowadays highly
parallelized but more RISC than CISC).

Wirth's processor illustrates the features a CPU needs:
- starting with a basic "Von Neumann architecture"
  (allowing for JIT compilers not possible with a "pure Harvard
- adding indirect addressing
- adding memory mapped IO

But you are right the "Von Neumann bottleneck" is not covered. E.g. modern
processors have instruction cache and branch predictors to alleviate this
bottleneck a little bit.

But who knows: Wirth started with RISCO0, is now at RISC5. Perhaps an
upcoming RISC6 will introduce instruction cache making it a modern "modified
Harvard architecture".


-----Original Message-----
From: Jan Verhoeven [mailto:jan at verhoeven272.nl] 
Sent: Mittwoch, 5. März 2014 15:30
To: ETH Oberon and related systems
Subject: Re: [Oberon] FPGA Oberon some news and a reply to F.P.

Claudio Nieder wrote:
> What is the point of inventing something new just for the explanation 
> of the CPU instruction set? It's not that you use it when programming. 
> When programming you use Oberon all the time. claudio 

Yes you are right. We should have stuck to Cobol and Fortran. All the 
successors were just useless inventions just for the explanation of 
language keywords.


Jan Verhoeven

Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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