[Oberon] FPGA Oberon some news and a reply to F.P.
jan at verhoeven272.nl
Wed Mar 5 19:58:01 CET 2014
No no, the 6502 was a second generation CISC CPU. The first RISC was
probably the MIPS and perhaps the first ARM cpu used in the Archimedes.
The MicroChip PIC was the first RISC processor to enter the market on a
large scale in the early 90's. And of course the Atmel AVR. And more later.
What I am disappointed about is the fact that Wirth fell back to
undecipherable mnemonics for his newly defined CPU.
The 6502 and 6800 were known for their BRA's. Intel 8080 was not much
better with their DAD and LXI. The guys at Zilog used more letters and
better acronyms: LD and RET. Zilog source code is one of the easiest to
read back. Even after 30 years.
The 8086 is good readable too, as long as you reverse the operands...
Intel moves backwards.
PIC uses CLR, SUBWF, INCF etc which has a very steep learning curve. The
AVR is a bit like the 6xxx series but not too hard to learn.
And then came RISC5 which gave us mnemonics that look like the
predecessor of the 6800...
And, worst of all, WHY would you want to fall back to mnemonics? Why do
you need to use
MOV 1, 2 (which looks stupid)
when you can also use
Load R1, 2 (which looks logical)
or, even better:
R1 := 2 (which leaves no doubt at all)
Mnemonics were inevitable in times when RAM was priced per bit and cpu
clocks were measured in kHz.
Until now, the future started in Zurich. Mnemonics are a thing from the
past. We don't need them anymore. We have fast processors with more RAM
than my first HDD.
I didn't see any jump, call and return instructions in the specification
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