[Oberon] RISC5

Paul Reed paulreed at paddedcell.com
Tue Apr 15 15:10:04 CEST 2014

Dear Joerg,

> By definition, Project Oberon works on the imaginary RISCv5.
> NW emulated his RISCv5 on an FPGA HW
> PdW emulated the RISCv5 in C and SDL on arbiträry HW
> Short: Project Oberon is ALWAYS emulated as there is no real RISCv5 HW.

That's rubbish.  The RISC5 is implemented in hardware.


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